Microchip ATMEGA48A-AU, 8 bit 8 Bit MCU, Atmega Microcontroller, 20 MHz, 4kB EEPROM, 32-Pin TQFP
- RS Stock No.:
- 352-150
- Mfr. Part No.:
- ATMEGA48A-AU
- Brand:
- Microchip
Subtotal (1 bag of 2 units)*
$7.81
(exc. GST)
$8.592
(inc. GST)
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In Stock
- Plus 500 unit(s) shipping from 19 January 2026
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Units | Per unit | Per Bag* |
|---|---|---|
| 2 + | $3.905 | $7.81 |
*price indicative
- RS Stock No.:
- 352-150
- Mfr. Part No.:
- ATMEGA48A-AU
- Brand:
- Microchip
Specifications
Technical data sheets
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Microchip | |
| Series | Atmega | |
| Product Type | Microcontroller | |
| Package Type | TQFP | |
| Pin Count | 32 | |
| Device Core | 8 Bit MCU | |
| Data Bus Width | 8bit | |
| Program Memory Size | 4kB | |
| Interface Type | SPI, 2 Wire | |
| Maximum Clock Frequency | 20MHz | |
| RAM Size | 2kB | |
| Maximum Supply Voltage | 5.5V | |
| Number of Programmable I/Os | 23 | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 85°C | |
| Standards/Approvals | RoHS | |
| Minimum Supply Voltage | 1.8V | |
| Program Memory Type | EEPROM | |
| Number of Timers | 3 | |
| ADCs | 10 Bit | |
| Instruction Set Architecture | Advanced RISC Architecture | |
| Select all | ||
|---|---|---|
Brand Microchip | ||
Series Atmega | ||
Product Type Microcontroller | ||
Package Type TQFP | ||
Pin Count 32 | ||
Device Core 8 Bit MCU | ||
Data Bus Width 8bit | ||
Program Memory Size 4kB | ||
Interface Type SPI, 2 Wire | ||
Maximum Clock Frequency 20MHz | ||
RAM Size 2kB | ||
Maximum Supply Voltage 5.5V | ||
Number of Programmable I/Os 23 | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 85°C | ||
Standards/Approvals RoHS | ||
Minimum Supply Voltage 1.8V | ||
Program Memory Type EEPROM | ||
Number of Timers 3 | ||
ADCs 10 Bit | ||
Instruction Set Architecture Advanced RISC Architecture | ||
The Microchip low power CMOS 8-bit microcontrollers based on the AVR enhanced RISC architecture. By executing instructions in a single clock cycle, the devices achieve CPU throughput approaching one million instructions per second (MIPS) per megahertz, allowing the system designer to optimize power consumption versus processing speed.
Write or erase cycles 10000 flash 100000 EEPROM
Data retention 20 years at 85C 100 years at 25C
Optional boot code section with independent lock bits
In-system programming by on-chip boot program
True read-while-write operation
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