Nexperia 74HCT165D,653 1 Surface Shift Register 74HCT SO, 16-Pin
- RS Stock No.:
- 170-8015
- Mfr. Part No.:
- 74HCT165D,653
- Brand:
- Nexperia
Bulk discount available
Subtotal (1 reel of 2500 units)*
$780.00
(exc. GST)
$857.50
(inc. GST)
FREE delivery for orders over $60.00 ex GST
Temporarily out of stock
- Shipping from 11 September 2026
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Units | Per unit | Per Reel* |
|---|---|---|
| 2500 - 10000 | $0.312 | $780.00 |
| 12500 + | $0.28 | $700.00 |
*price indicative
- RS Stock No.:
- 170-8015
- Mfr. Part No.:
- 74HCT165D,653
- Brand:
- Nexperia
Specifications
Technical data sheets
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Nexperia | |
| Product Type | Shift Register | |
| Package Type | SO | |
| Logic Family | 74HCT | |
| Mount Type | Surface | |
| Number of Elements | 1 | |
| Minimum Supply Voltage | 4.5V | |
| Pin Count | 16 | |
| Maximum Supply Voltage | 5.5V | |
| Trigger Type | Positive Edge | |
| Maximum Operating Temperature | 125°C | |
| Standards/Approvals | No | |
| Width | 4 mm | |
| Length | 10mm | |
| Height | 1.75mm | |
| Series | 74HCT165 | |
| Automotive Standard | No | |
| Select all | ||
|---|---|---|
Brand Nexperia | ||
Product Type Shift Register | ||
Package Type SO | ||
Logic Family 74HCT | ||
Mount Type Surface | ||
Number of Elements 1 | ||
Minimum Supply Voltage 4.5V | ||
Pin Count 16 | ||
Maximum Supply Voltage 5.5V | ||
Trigger Type Positive Edge | ||
Maximum Operating Temperature 125°C | ||
Standards/Approvals No | ||
Width 4 mm | ||
Length 10mm | ||
Height 1.75mm | ||
Series 74HCT165 | ||
Automotive Standard No | ||
The 74HC165, 74HCT165 are high-speed Si-gate CMOS devices. They are pin compatible with Low-power Schottky TTL (LSTTL). The 74HC165, 74HCT165 are 8-bit parallel-load or serial-in shift registers with complementary serial outputs (Q7 and Q7) available from the last stage. When the parallel load (PL) input is LOW, parallel data from the D0 to D7 inputs are loaded into the register asynchronously. When PL is HIGH, data enters the register serially at the DS input and shifts one place to the right (Q0 → Q1 → Q2, etc.) with each positive-going clock transition. This feature allows parallel-to-serial converter expansion by tying the Q7 output to the DS input of the succeeding stage. The clock input is a gated-OR structure which allows one input to be used as an active LOW clock enable (CE) input.
Simple control interface
I/O expansion
Asynchronous and synchronous load options
High frequency
Cascadable
LED drivers
Key applications
Displays
Control units