Infineon SRAM- 128 MB
- RS Stock No.:
- 273-5438
- Mfr. Part No.:
- S70KL1282GABHV020
- Brand:
- Infineon
This image is representative of the product range
Bulk discount available
Subtotal (1 unit)*
$8.96
(exc. GST)
$9.86
(inc. GST)
FREE delivery for orders over $60.00 ex GST
Limited stock
- 1 left, ready to ship from another location
Need more? Click ‘Check delivery dates’ to find extra stock and lead times.
Units | Per unit |
|---|---|
| 1 - 9 | $8.96 |
| 10 - 24 | $8.25 |
| 25 - 49 | $7.95 |
| 50 - 99 | $7.79 |
| 100 + | $7.24 |
*price indicative
- RS Stock No.:
- 273-5438
- Mfr. Part No.:
- S70KL1282GABHV020
- Brand:
- Infineon
Specifications
Technical data sheets
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Infineon | |
| Product Type | SRAM | |
| Memory Size | 128MB | |
| Number of Bits per Word | 16 | |
| Maximum Random Access Time | 35ns | |
| Maximum Clock Frequency | 200MHz | |
| Minimum Supply Voltage | 1.8V | |
| Timing Type | DDR | |
| Maximum Supply Voltage | 3V | |
| Minimum Operating Temperature | -40°C | |
| Package Type | FBGA-24 Ball | |
| Maximum Operating Temperature | 105°C | |
| Series | HYPERRAM | |
| Standards/Approvals | No | |
| Automotive Standard | AEC-Q100 | |
| Select all | ||
|---|---|---|
Brand Infineon | ||
Product Type SRAM | ||
Memory Size 128MB | ||
Number of Bits per Word 16 | ||
Maximum Random Access Time 35ns | ||
Maximum Clock Frequency 200MHz | ||
Minimum Supply Voltage 1.8V | ||
Timing Type DDR | ||
Maximum Supply Voltage 3V | ||
Minimum Operating Temperature -40°C | ||
Package Type FBGA-24 Ball | ||
Maximum Operating Temperature 105°C | ||
Series HYPERRAM | ||
Standards/Approvals No | ||
Automotive Standard AEC-Q100 | ||
The Infineon DRAM is a high speed CMOS self refresh DRAM, with HYPERBUS™ interface. The DRAM array uses dynamic cells that require periodic refresh. Refresh control logic within the device manages the refresh operations on the DRAM array when the memory is not being actively read or written by the HYPERBUS™ interface master. Since the host is not required to manage any refresh operations, the DRAM array appears to the host as though the memory uses static cells that retain data without refresh. Hence, the memory is more accurately described as pseudo static RAM.
HYPERBUS™ interface
200 MHz maximum clock rate
Configurable burst characteristics
Data throughput up to 400 MBps
Bidirectional read write data strobe
Optional DDR centre aligned read strobe