Nexperia 74HC73D-Q100J Flip Flop IC HC, CMOS, 14-Pin SO-14
- RS Stock No.:
- 243-4415
- Mfr. Part No.:
- 74HC73D-Q100J
- Brand:
- Nexperia
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View bulk pricing optionsSubtotal (1 reel of 2500 units)*
$937.50
(exc. GST)
$1,030.00
(inc. GST)
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Units | Per unit | Per Reel* |
|---|---|---|
| 2500 - 10000 | $0.375 | $937.50 |
| 12500 + | $0.338 | $845.00 |
*price indicative
- RS Stock No.:
- 243-4415
- Mfr. Part No.:
- 74HC73D-Q100J
- Brand:
- Nexperia
Specifications
Technical data sheets
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Nexperia | |
| Product Type | Flip Flop IC | |
| Logic Family | HC | |
| Input Type | Single Ended | |
| Output Type | CMOS | |
| Polarity | Negative | |
| Mount Type | Surface | |
| Minimum Supply Voltage | 2V | |
| Package Type | SO-14 | |
| Pin Count | 14 | |
| Maximum Supply Voltage | 6V | |
| Flip-Flop Type | JK Type | |
| Trigger Type | Negative Edge | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 125°C | |
| Series | 74HC73-Q100 | |
| Standards/Approvals | HBM JESD22-A114F, AEC-Q100 (Grade 1), JEDEC Standards JESD8C (2.7 V to 3.6 V), JESD7A (2.0 V to 6.0 V), MM JESD22-A115-A | |
| Automotive Standard | AEC-Q100 Grade 1 | |
| Select all | ||
|---|---|---|
Brand Nexperia | ||
Product Type Flip Flop IC | ||
Logic Family HC | ||
Input Type Single Ended | ||
Output Type CMOS | ||
Polarity Negative | ||
Mount Type Surface | ||
Minimum Supply Voltage 2V | ||
Package Type SO-14 | ||
Pin Count 14 | ||
Maximum Supply Voltage 6V | ||
Flip-Flop Type JK Type | ||
Trigger Type Negative Edge | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 125°C | ||
Series 74HC73-Q100 | ||
Standards/Approvals HBM JESD22-A114F, AEC-Q100 (Grade 1), JEDEC Standards JESD8C (2.7 V to 3.6 V), JESD7A (2.0 V to 6.0 V), MM JESD22-A115-A | ||
Automotive Standard AEC-Q100 Grade 1 | ||
The Nexperia dual negative edge triggered JK flip-flop with individual J, K, clock (nCP) and reset (nR) inputs and complementary nQ and nQ outputs. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. (nR) is asynchronous, when LOW it overrides the clock and data inputs, forcing the nQ output LOW and the nQ output high. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
CMOS low-power dissipation
Wide supply voltage range from 2.0 to 6.0 V
High noise immunity
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
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