Toshiba 74HC138D, Decoder, 16-Pin SOIC
- RS Stock No.:
- 171-3556
- Mfr. Part No.:
- 74HC138D
- Brand:
- Toshiba
This image is representative of the product range
Bulk discount available
Subtotal (1 pack of 50 units)*
$16.75
(exc. GST)
$18.40
(inc. GST)
Add 200 units to get free delivery
In Stock
- Plus 500 unit(s) shipping from 04 February 2026
- Plus 8,500 unit(s) shipping from 11 February 2026
Need more? Click ‘Check delivery dates’ to find extra stock and lead times.
Units | Per unit | Per Pack* |
|---|---|---|
| 50 - 600 | $0.335 | $16.75 |
| 650 - 1200 | $0.327 | $16.35 |
| 1250 + | $0.322 | $16.10 |
*price indicative
- RS Stock No.:
- 171-3556
- Mfr. Part No.:
- 74HC138D
- Brand:
- Toshiba
Specifications
Technical data sheets
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Toshiba | |
| Logic Family | 74HC | |
| Product Type | Decoder | |
| Number of Inputs | 3 | |
| Logic Function | Decoder | |
| Mount Type | Surface | |
| Package Type | SOIC | |
| Number of Outputs | 34 | |
| Pin Count | 16 | |
| Minimum Supply Voltage | 2V | |
| Maximum Supply Voltage | 6V | |
| Minimum Operating Temperature | 125°C | |
| Maximum Operating Temperature | -40°C | |
| Series | 74HC | |
| Length | 10.2mm | |
| Width | 4 mm | |
| Standards/Approvals | No | |
| Height | 1.75mm | |
| Automotive Standard | No | |
| Select all | ||
|---|---|---|
Brand Toshiba | ||
Logic Family 74HC | ||
Product Type Decoder | ||
Number of Inputs 3 | ||
Logic Function Decoder | ||
Mount Type Surface | ||
Package Type SOIC | ||
Number of Outputs 34 | ||
Pin Count 16 | ||
Minimum Supply Voltage 2V | ||
Maximum Supply Voltage 6V | ||
Minimum Operating Temperature 125°C | ||
Maximum Operating Temperature -40°C | ||
Series 74HC | ||
Length 10.2mm | ||
Width 4 mm | ||
Standards/Approvals No | ||
Height 1.75mm | ||
Automotive Standard No | ||
The 74HC138D is a high speed CMOS 3-to-8 DECODER fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. When the device is enabled, 3 Binary Select inputs (A, B and C) determine which one of the outputs (Y0 - Y7) will go low. When enable input G1 is held low or either G2A or G2B is held high, decoding function is inhibited and alloutputs go high.G1, G2A, and G2B inputs are provided to ease cascade connection and for use as an address decoder for memory systems. All inputs are equipped with protection circuits against static discharge or transient excess voltage
High speed: tpd = 16 ns (typ.) at VCC = 5 V
Low power dissipation: ICC = 4.0 μA (max) at Ta = 25
Balanced propagation delays: tPLH ≈ tPHL
Wide operating voltage range: VCC(opr) = 2.0 to 6.0 V