Maxim Integrated, Dual 10 bit- ADC 100Msps, 48-Pin TQFN-EP

Very-Low-Power Operation (57mW/Channel at 100Msps)
1.8V or 2.5V to 3.3V Analog Supply
Excellent Dynamic Performance
60dBFS SNR at 70MHz
82dBc SFDR at 70MHz
User-Programmable Adjustments and Feature Selection through an SPI™ Interface
Selectable Data Bus (Dual CMOS or Single Multiplexed CMOS)
DCLK Output and Programmable Data Output Timing Simplifies High-Speed Digital Interface
Very Wide Input Common-Mode Voltage Range (0.4V to 1.4V)
Very High Analog Input Bandwidth (> 850MHz)
Single-Ended or Differential Analog Inputs
Single-Ended or Differential Clock Input
Divide-by-One (DIV1), Divide-by-Two (DIV2), and Divide-by-Four (DIV4) Clock Modes
Two's Complement, Gray Code, and Offset Binary Output Data Format
Out-of-Range Indicator (DOR)
CMOS Output Internal Termination Options (Programmable)
Reversible Bit Order (Programmable)
Data Output Test Patterns
Small 7mm x 7mm 48-Pin Thin QFN Package with Exposed Pad
Applications
Digital Set-Top Boxes
IF and Baseband Communications, Including Cellular Base Stations and Point-to-Point Microwave Receivers
Portable Instrumentation and Low-Power Data Acquisition
Ultrasound and Medical Imaging

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