Alliance Memory AS4C128M8D3B-12BINTR SDRAM 1 GB Surface, 78-Pin 8 bit FBGA-78 Ball
- RS Stock No.:
- 425-150
- Mfr. Part No.:
- AS4C128M8D3B-12BINTR
- Brand:
- Alliance Memory
Subtotal (1 reel of 2500 units)*
$85,865.00
(exc. GST)
$94,452.50
(inc. GST)
Stock information currently inaccessible - Please check back later
Units | Per unit | Per Reel* |
|---|---|---|
| 2500 + | $34.346 | $85,865.00 |
*price indicative
- RS Stock No.:
- 425-150
- Mfr. Part No.:
- AS4C128M8D3B-12BINTR
- Brand:
- Alliance Memory
Specifications
Technical data sheets
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Alliance Memory | |
| Product Type | SDRAM | |
| Memory Size | 1GB | |
| Organisation | 128M x 8 | |
| Data Bus Width | 8bit | |
| Number of Bits per Word | 8 | |
| Maximum Clock Frequency | 800MHz | |
| Maximum Random Access Time | 20ns | |
| Mount Type | Surface | |
| Package Type | FBGA-78 Ball | |
| Minimum Operating Temperature | -40°C | |
| Pin Count | 78 | |
| Maximum Operating Temperature | 95°C | |
| Series | AS4C128M8D3B | |
| Length | 10.5mm | |
| Standards/Approvals | RoHS, JEDEC | |
| Width | 8mm | |
| Height | 1mm | |
| Minimum Supply Voltage | 1.43V | |
| Maximum Supply Voltage | 1.5V | |
| Automotive Standard | No | |
| Select all | ||
|---|---|---|
Brand Alliance Memory | ||
Product Type SDRAM | ||
Memory Size 1GB | ||
Organisation 128M x 8 | ||
Data Bus Width 8bit | ||
Number of Bits per Word 8 | ||
Maximum Clock Frequency 800MHz | ||
Maximum Random Access Time 20ns | ||
Mount Type Surface | ||
Package Type FBGA-78 Ball | ||
Minimum Operating Temperature -40°C | ||
Pin Count 78 | ||
Maximum Operating Temperature 95°C | ||
Series AS4C128M8D3B | ||
Length 10.5mm | ||
Standards/Approvals RoHS, JEDEC | ||
Width 8mm | ||
Height 1mm | ||
Minimum Supply Voltage 1.43V | ||
Maximum Supply Voltage 1.5V | ||
Automotive Standard No | ||
- COO (Country of Origin):
- TW
The Alliance Memory 1Gb Double-Data-Rate-3 DRAMs is double data rate architecture to achieve high-speed operation. The chip is designed to comply with all key DDR3 DRAM key features and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks.
Write Leveling
ZQ Calibration
RoHS compliant
Auto Refresh and Self Refresh
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