STMicroelectronics STM32MP231AAJ3 ARM Cortex A35, ARM Cortex M33 Microprocessor STM32MP23xA/D 16 bit Arm Cortex, ARM
- RS Stock No.:
- 482-980
- Mfr. Part No.:
- STM32MP231AAJ3
- Brand:
- STMicroelectronics
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- RS Stock No.:
- 482-980
- Mfr. Part No.:
- STM32MP231AAJ3
- Brand:
- STMicroelectronics
Specifications
Technical data sheets
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | STMicroelectronics | |
| Product Type | Microprocessor | |
| Series | STM32MP23xA/D | |
| Device Core | ARM Cortex A35, ARM Cortex M33 | |
| Data Bus Width | 16bit | |
| Instruction Set Architecture | Arm Cortex, ARM V8-M, 64 Bit | |
| Maximum Clock Frequency | 1.5GHz | |
| Interface Type | UART, SDM, SAI, SPI, USB 2.0, SPDIF, USART, I2C, I3C, DDR4, CAN, Ethernet, NAND, DDR3L, FMC, LPDDR4 | |
| Package Type | TFBGA361 | |
| Minimum Supply Voltage | 1.71V | |
| Pin Count | 361 | |
| Maximum Supply Voltage | 3.6V | |
| Standards/Approvals | IEEE 1588v2, JEDEC, ECOPACK2 | |
| Number of Cores | 2 | |
| Automotive Standard | No | |
| Select all | ||
|---|---|---|
Brand STMicroelectronics | ||
Product Type Microprocessor | ||
Series STM32MP23xA/D | ||
Device Core ARM Cortex A35, ARM Cortex M33 | ||
Data Bus Width 16bit | ||
Instruction Set Architecture Arm Cortex, ARM V8-M, 64 Bit | ||
Maximum Clock Frequency 1.5GHz | ||
Interface Type UART, SDM, SAI, SPI, USB 2.0, SPDIF, USART, I2C, I3C, DDR4, CAN, Ethernet, NAND, DDR3L, FMC, LPDDR4 | ||
Package Type TFBGA361 | ||
Minimum Supply Voltage 1.71V | ||
Pin Count 361 | ||
Maximum Supply Voltage 3.6V | ||
Standards/Approvals IEEE 1588v2, JEDEC, ECOPACK2 | ||
Number of Cores 2 | ||
Automotive Standard No | ||
- COO (Country of Origin):
- TW
The STMicroelectronics High performance single or dual-core Arm Cortex-A35 64-bit RISC core operating at up to 1.5 GHz. The Cortex‑A35 processor includes a 32-Kbyte L1 instruction cache for each CPU, a 32-Kbyte L1 data cache for each CPU, and a 512-Kbyte L2 cache. The Cortex‑A35 processor uses a highly efficient 8-stage in-order pipeline that has been extensively optimized to provide full Armv8-A features while maximizing area and power efficiency.
Four USARTs and three UARTs
One Low power UART
Four SAI serial audio interfaces
One SPDIF Rx interface
Three SDMMC interfaces
USB 2.0 Host with embedded Hi-Speed PHY
USB 2.0 dual-role data with Hi-Speed PHYs
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