Nexperia 74LVC273PW,118 1 Flip Flop IC 74LVC, D Type, 20-Pin TSSOP
- RS Stock No.:
- 170-5348
- Mfr. Part No.:
- 74LVC273PW,118
- Brand:
- Nexperia
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Units | Per unit | Per Pack* |
|---|---|---|
| 25 - 600 | $0.372 | $9.30 |
| 625 - 1225 | $0.363 | $9.08 |
| 1250 + | $0.358 | $8.95 |
*price indicative
- RS Stock No.:
- 170-5348
- Mfr. Part No.:
- 74LVC273PW,118
- Brand:
- Nexperia
Specifications
Technical data sheets
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Nexperia | |
| Product Type | Flip Flop IC | |
| Logic Family | 74LVC | |
| Input Type | Single Ended | |
| Output Type | D Type | |
| Clock Frequency | 150MHz | |
| Polarity | Non-Inverting | |
| Mount Type | Surface | |
| Minimum Supply Voltage | 1.65V | |
| Package Type | TSSOP | |
| Pin Count | 20 | |
| Maximum Supply Voltage | 3.6V | |
| Maximum Propagation Delay Time @ CL | 10.5ns | |
| Minimum Operating Temperature | -40°C | |
| Flip-Flop Type | D Flip-Flop | |
| Trigger Type | Positive Edge | |
| Maximum Operating Temperature | 125°C | |
| Number of Elements per Chip | 1 | |
| Standards/Approvals | No | |
| Length | 6.6mm | |
| Height | 950μm | |
| Automotive Standard | No | |
| Select all | ||
|---|---|---|
Brand Nexperia | ||
Product Type Flip Flop IC | ||
Logic Family 74LVC | ||
Input Type Single Ended | ||
Output Type D Type | ||
Clock Frequency 150MHz | ||
Polarity Non-Inverting | ||
Mount Type Surface | ||
Minimum Supply Voltage 1.65V | ||
Package Type TSSOP | ||
Pin Count 20 | ||
Maximum Supply Voltage 3.6V | ||
Maximum Propagation Delay Time @ CL 10.5ns | ||
Minimum Operating Temperature -40°C | ||
Flip-Flop Type D Flip-Flop | ||
Trigger Type Positive Edge | ||
Maximum Operating Temperature 125°C | ||
Number of Elements per Chip 1 | ||
Standards/Approvals No | ||
Length 6.6mm | ||
Height 950μm | ||
Automotive Standard No | ||
- COO (Country of Origin):
- CN
The 74LVC273 has eight edge-triggered, D-type flip-flops with individual Dn inputs and Qn outputs. The common clock (CP) and Master reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The state of each Dn input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the flip-flop. All outputs will be forced LOW independently of clock or data inputs by a LOW voltage level on the MR input.
Mixed 5 V and 3.3 V applications
Improved signal integrity with integrated termination resistors
High noise immunity
Flow through pin out for easy layout
Wide supply voltage range
Low propagation delay
Overvoltage tolerant input options
Integrated source termination resistor options
Bus hold options
Frequency division
Controlled delays
Interface between asynchronous and synchronous systems
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