Microchip, 48-Pin QFN, Ethernet Transceiver, 3.3 V RGMII 3.3V KSZ9031RNXIC, Full Duplex/Half Duplex

RS Stock No.:: 177-3549
Mfr. Part No.:: KSZ9031RNXIC
Brand:: Microchip

Microchip, 48-Pin QFN, Ethernet Transceiver, 3.3 V RGMII 3.3V KSZ9031RNXIC, Full Duplex/Half Duplex

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Units	Per unit	Per Tray*	Saving
260 - 1040	$5.263	$1,368.38	-
1300 +	$4.736	$1,231.36	$685.10

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RS Stock No.:: 177-3549
Mfr. Part No.:: KSZ9031RNXIC
Brand:: Microchip

Specifications

Technical data sheets

Legislation and Compliance

Product Details

Find similar products by selecting one or more attributes.

Select all	Attribute	Value
	Brand	Microchip
	Product Type	Ethernet Transceiver
	Communication Mode	Full Duplex/Half Duplex
	Loopback Mode	Internal
	Interface Type	RGMII
	Standard Supported	10BASE-T, IEEE 802.3, 100BASE-TX, 1000BASE-T
	Mount Type	Surface
	Package Type	QFN
	Pin Count	48
	Maximum Supply Voltage	3.3V
	Minimum Operating Temperature	-40°C
	Maximum Operating Temperature	85°C
	Standards/Approvals	No
	Width	7mm
	Height	800μm
	Length	7mm
	Minimum Supply Voltage	3.3V
	Supply Current	210mA
	Automotive Standard	AEC-Q100

	Select all
	Brand Microchip
	Product Type Ethernet Transceiver
	Communication Mode Full Duplex/Half Duplex
	Loopback Mode Internal
	Interface Type RGMII
	Standard Supported 10BASE-T, IEEE 802.3, 100BASE-TX, 1000BASE-T
	Mount Type Surface
	Package Type QFN
	Pin Count 48
	Maximum Supply Voltage 3.3V
	Minimum Operating Temperature -40°C
	Maximum Operating Temperature 85°C
	Standards/Approvals No
	Width 7mm
	Height 800μm
	Length 7mm
	Minimum Supply Voltage 3.3V
	Supply Current 210mA
	Automotive Standard AEC-Q100

Datasheet

COO (Country of Origin):: US

The KSZ9031 reduces board cost and simplifies board layout by using on-chip termination resistors for the four differential pairs and by integrating an LDO controller to drive a low-cost MOSFET to supply the 1.2V core.

Single-chip 10/100/1000Mbps Ethernet transceiver

KSZ9031Mxx feature GMII/MII standard Interface with 3.3V/2.5V/1.8V tolerant I/Os

KSZ9031Rxx feature RGMII timing supports on-chip delay according to RGMII Version 2.0, with programming options for external delay and making adjustments and corrections to TX and RX timing paths

GMII/MII/RGMII with 3.3V/2.5V/1.8V tolerant I/Os

Auto-negotiation to automatically select the highest linkup speed (10/100/1000Mbps) and duplex (half/full)

On-chip termination resistors for the differential pairs

On-chip LDO controller to support single 3.3V supply operation – requires only one external FET to generate 1.2V for the core

Jumbo frame support up to 16KB

125MHz Reference Clock Output

Energy-detect power-down mode