49FCT3805APYG, Clock Divider CMOS, 2-Input, 20-Pin SSOP

The Renesas Electronics buffer/non-inverting clock driver built using advanced dual metal CMOS technology. The device consists of two banks of drivers, each with a 1:5 fanout and its own output enable control. The device has a heartbeat monitor for diagnostics and PLL driving. The MON output is identical to all other outputs and complies with the output specifications in this document. It offers low capacitance inputs with hysteresis. It is designed for high speed clock distribution where signal quality and skew are critical. It is also allows single point-topoint transmission line driving in applications such as address distribution, where one signal must be distributed to multiple recievers with low skew and high signal quality.

0.5 MICRON CMOS technology
Guaranteed low skew < 500ps (max.)
Very low duty cycle distortion < 1.0ns (max.)
Very low CMOS power levels
TTL compatible inputs and outputs
Inputs can be driven from 3.3V or 5V components
Two independent output banks with 3-state control
Available in SSOP, SOIC, and QSOP packages

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