Renesas Electronics 9DB633AGILF Clock Buffer 28-Pin TSSOP
- RS Stock No.:
- 263-7988
- Mfr. Part No.:
- 9DB633AGILF
- Brand:
- Renesas Electronics
Bulk discount available
Subtotal (1 unit)*
$9.30
(exc. GST)
$10.23
(inc. GST)
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- Shipping from 06 April 2026
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Units | Per unit |
|---|---|
| 1 - 9 | $9.30 |
| 10 - 24 | $8.36 |
| 25 - 49 | $8.18 |
| 50 - 99 | $7.91 |
| 100 + | $6.85 |
*price indicative
- RS Stock No.:
- 263-7988
- Mfr. Part No.:
- 9DB633AGILF
- Brand:
- Renesas Electronics
Specifications
Technical data sheets
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Renesas Electronics | |
| Number of Elements per Chip | 5 | |
| Maximum Supply Current | 200 μA | |
| Maximum Input Frequency | 110MHz | |
| Mounting Type | Surface Mount | |
| Package Type | TSSOP | |
| Pin Count | 28 | |
| Select all | ||
|---|---|---|
Brand Renesas Electronics | ||
Number of Elements per Chip 5 | ||
Maximum Supply Current 200 μA | ||
Maximum Input Frequency 110MHz | ||
Mounting Type Surface Mount | ||
Package Type TSSOP | ||
Pin Count 28 | ||
- COO (Country of Origin):
- TW
The Renesas Electronics zero-delay buffer supports PCIe Gen1 and Gen2 clocking requirements. It is driven by a differential SRC output pair from an IDT main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without spread-spectrum clocking.
SMBus Interface
Selectable PLL bandwidth
Minimizes jitter peaking in downstream PLLs
Cycle-to-cycle jitter < 50ps
Output-to-output skew < 50 ps
PCIe Gen3 phase jitter < 1.0ps RMS
Selectable PLL bandwidth
Minimizes jitter peaking in downstream PLLs
Cycle-to-cycle jitter < 50ps
Output-to-output skew < 50 ps
PCIe Gen3 phase jitter < 1.0ps RMS
For these non-cancellable (NC), and non-returnable (NR) products, Terms and Conditions apply.
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