Microchip Technology ATF22LV10C-10JU, SPLD Simple Programmable Logic Device ATF22LV10C 350 Gates, 10 Macro Cells,

  • RS Stock No. 127-8211
  • Mfr. Part No. ATF22LV10C-10JU
  • Manufacturer Microchip
Technical data sheets
Legislation and Compliance
RoHS Certificate of Compliance
COO (Country of Origin): PH
Product Details

Simple Programmable Logic Device, Microchip

From Atmel, this high-performance programmable logic device boasts low power, high reliability and an industry standard architecture.

Specifications
Attribute Value
Family Name ATF22LV10C
Number of Gates 350
Number of Macro Cells 10
Number of User I/Os 10
Maximum Internal Frequency 83.3MHz
Re-programmability Support Yes
Mounting Type Surface Mount
Package Type PLCC
Pin Count 28
Maximum Propagation Delay Time 10ns
Fabrication Technology CMOS, TTL
Dimensions 11.58 x 11.58 x 4.06mm
Height 4.06mm
Minimum Operating Supply Voltage 3 V
Minimum Operating Temperature 0 °C
Width 11.58mm
Maximum Operating Temperature +80 °C
Length 11.58mm
Maximum Operating Supply Voltage 5.5 V
Propagation Delay Test Condition 35pF
375 In stock for delivery within 7 working day(s) (Global Stock)
Price (ex. GST) Each (In a Pack of 5)
$ 2.20
(exc. GST)
$ 2.42
(inc. GST)
units
Per unit
Per Pack*
5 - 20
$2.20
$11.00
25 - 95
$2.154
$10.77
100 - 495
$2.124
$10.62
500 - 995
$2.048
$10.24
1000 +
$1.978
$9.89
*price indicative
Packaging Options:
Related Products
The Microchip Technology ATF1504AS family, PLCC package, surface ...
Description:
The Microchip Technology ATF1504AS family, PLCC package, surface mount, 84-pin, high performance, a high-density complex programmable logic device (CPLD) is an electrically erasable device It has a voltage rating between 3.3V and 5V. The (CPLD) is designed with 64 logic ...
Field Programmable Gate Arrays, Xilinx An FPGA is ...
Description:
Field Programmable Gate Arrays, Xilinx An FPGA is a semiconductor device consisting of a matrix of Configurable Logic Blocks (CLBs) connected through programmable interconnects. The user determines these interconnections by programming SRAM. A CLB can be simple (AND, OR gates, ...