Cypress Semiconductor NOR 64Mbit CFI Flash Memory 56-Pin TSOP, S29GL064S70TFI020
- RS Stock No.:
- 193-8831
- Mfr. Part No.:
- S29GL064S70TFI020
- Brand:
- Cypress Semiconductor
Unavailable
RS will no longer stock this product.
- RS Stock No.:
- 193-8831
- Mfr. Part No.:
- S29GL064S70TFI020
- Brand:
- Cypress Semiconductor
Specifications
Technical data sheets
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Cypress Semiconductor | |
| Memory Size | 64Mbit | |
| Interface Type | CFI | |
| Package Type | TSOP | |
| Pin Count | 56 | |
| Organisation | 8M x 8 bit | |
| Mounting Type | Surface Mount | |
| Cell Type | NOR | |
| Minimum Operating Supply Voltage | 2.7 V | |
| Maximum Operating Supply Voltage | 3.6 V | |
| Dimensions | 18.5 x 14.1 x 1.05mm | |
| Minimum Operating Temperature | -40 °C | |
| Number of Words | 8M | |
| Maximum Random Access Time | 70ns | |
| Maximum Operating Temperature | +85 °C | |
| Number of Bits per Word | 8bit | |
| Select all | ||
|---|---|---|
Brand Cypress Semiconductor | ||
Memory Size 64Mbit | ||
Interface Type CFI | ||
Package Type TSOP | ||
Pin Count 56 | ||
Organisation 8M x 8 bit | ||
Mounting Type Surface Mount | ||
Cell Type NOR | ||
Minimum Operating Supply Voltage 2.7 V | ||
Maximum Operating Supply Voltage 3.6 V | ||
Dimensions 18.5 x 14.1 x 1.05mm | ||
Minimum Operating Temperature -40 °C | ||
Number of Words 8M | ||
Maximum Random Access Time 70ns | ||
Maximum Operating Temperature +85 °C | ||
Number of Bits per Word 8bit | ||
The S29GL-S mid density family of devices are 3.0-volt single-power flash memory manufactured using 65 nm MirrorBit technology.
The S29GL064S is a 64-Mb device organized as 4,194,304 words or 8,388,608 bytes. Depending on the model number, the devices have 16bit wide data bus only, or a 16bit wide data bus that can also function as an 8bit wide data bus by using the BYTE# input.
The devices can be programmed either in the host system or in standard EPROM programmers. Access times as fast as 70 ns are available. Package offerings include 48pin TSOP, 56pin TSOP, 48-ball fine-pitch BGA, and 64-ball Fortified BGA, depending on model number. Each device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. Each device requires only a single 3.0-volt power supply for both read and write functions. In addition to a VCC input, a high-voltage accelerated program (ACC) feature is supported through increased voltage on the WP#/ACC or ACC input. This feature is intended to facilitate system production. Commands are written to the device using standard microprocessor write timing. Write cycles also internally latch addresses and data needed for the programming and erase operations.
The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory.
The Advanced Sector Protection features several levels of sector protection, which can disable both the program and erase operations in certain sectors.
The S29GL064S is a 64-Mb device organized as 4,194,304 words or 8,388,608 bytes. Depending on the model number, the devices have 16bit wide data bus only, or a 16bit wide data bus that can also function as an 8bit wide data bus by using the BYTE# input.
The devices can be programmed either in the host system or in standard EPROM programmers. Access times as fast as 70 ns are available. Package offerings include 48pin TSOP, 56pin TSOP, 48-ball fine-pitch BGA, and 64-ball Fortified BGA, depending on model number. Each device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. Each device requires only a single 3.0-volt power supply for both read and write functions. In addition to a VCC input, a high-voltage accelerated program (ACC) feature is supported through increased voltage on the WP#/ACC or ACC input. This feature is intended to facilitate system production. Commands are written to the device using standard microprocessor write timing. Write cycles also internally latch addresses and data needed for the programming and erase operations.
The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory.
The Advanced Sector Protection features several levels of sector protection, which can disable both the program and erase operations in certain sectors.