The Red Pitaya Platform: Enabling Flexible Low-Cost Instrumentation

Red Pitaya is a groundbreaking open-source single-board instrumentation and control platform that has the potential to replace many expensive laboratory and field instruments, and all at a fraction of the price of separate pieces of test equipment.

 

Initially, at least, test-and-measurement equipment such as oscilloscopes or signal generators provided fixed functionality and a limited set of capabilities. In more recent times, test and measurement equipment vendors have integrated DSPs to offer broader feature sets tailored for specific applications. However, the ability to program these instruments and determine the final feature set was always a restricted choice of the manufacturer; and even with a broader set of features, most instruments today often do not have the precise functionality required for specific projects. This is especially the case for researchers at institutes and universities that are developing large complex systems based on smaller subsystems, including instruments. In these cases, it is often essential to use instruments at much finer or higher-resolution levels than those planned by equipment vendors. Integration problems can arise in fast-feedback systems involving two or more instrument subsystems that require a hard-real-time response with very little jitter. And often the interfaces to instruments prove inadequate to achieve the required overall integrated system performance.

 

Red Pitaya

The new Red Pitaya initiative addresses these issues and makes it easy to develop many instrumentation variants inexpensively from a single platform, in conjunction with a unique open-source development ecosystem. Initially launched via a Kickstarter funding project, Red Pitaya is an open-source user-programmable and user-customizable signal-processing platform that combines Xilinx Zynq®-7010 SoC (System-on-Chip) based hardware with an open-source online repository of instrumentation applications.

The Zynq SoC combines a dual-core ARM® Cortex™-A9 processor with a wide selection of peripherals, plus Xilinx 7 series FPGA programmable logic, and delivers the foundation for a wide variety of instruments built from software apps available via an engineering community library known as the Bazaar cloud marketplace. In addition, the Red Pitaya Backyard repository hosts open-source development code and tools necessary for developing applications, along with the Spark Center and DesignSpark, which are resources for engineers to share and contribute new ideas and inputs for new Red Pitaya applications and hardware extension modules. The CPU runs the Linux operating system and supports the standard peripherals, such as Ethernet, USB OTG, Micro-SD storage and USB serial console. Red Pitaya can be programmed at different levels using various software interfaces including HDL, C/C++ and scripting languages. In addition, HTML-based interfaces enable access to Red Pitaya’s functionality in most web browsers from a tablet, smartphone or PC.

 

Hardware

As well as the Zynq SoC, the hardware platform features two fast 14-bit resolution 125-Msample/s analogue inputs using ADCs from Linear Technology; two fast 14-bit 125-Msample/s analogue outputs; four 12-bit 100ksample/s analogue inputs; four 12-bit 100ksample/s analogue outputs; a USB port; and an Ethernet port. The platform also has several expansion connectors for adding various types of hardware extension modules that can add analogue or digital ports or other capabilities. In addition, distributed processing is possible if several Red Pitaya modules are daisy-chained via fast serial connectors, enabling the building of a scalable complex system with the ability to add more inputs and outputs. The capabilities of the platform are shown in figure 1.

Figure 1 – The Red Pitaya instrument platform

 

An initial set of five open-source applications are available (designed to be stored in the on-board micro-SD card), which enable a two-channel 14-bit 125-Msample/s digital sampling oscilloscope; a two-channel 60MHz spectrum analyser with a waterfall diagram display; a two-channel 125MHz ARB (arbitrary waveform generator); a two-channel 60MHz frequency response analyser; and a two-channel PID (proportional, integral, derivative) controller.

The two-channel 125-Msample/s signal-acquisition and signal-generation capabilities can be combined with FPGA-based DSP processing in between to form hard-real-time feedback loops. The system also integrates several slower 100kHz I/O channels along with several digital I/Os.

 

Architecture

Figure 2 shows the system architecture of the Red Pitaya signal-processing system with multiple analogue and digital inputs and outputs.

 

Figure 2 – Red Pitaya system architecture

 

The platform follows the basic approach of modern signal-processing systems, whereby all the specifics of the processing and measurement system are concentrated in the digital domain. The approach is to be as simple and generic as possible at the analogue front-end and back-end electronics and to sample the signals with fast ADCs as soon as possible and send signals to the DACs as late as possible in the processing chain. The platform’s highly digital architecture enables the customization of hardware to perform a number of tasks across several applications, with possibilities only limited by the bandwidth of the analogue front- and back-end electronics and the computational resources of the processor and FPGA in the digital domain.

There are two main types of processing chains: the first is the ~50MHz bandwidth signal-processing chain, achieved by leveraging the extremely fast and low-jitter hard-real-time processing capabilities of FPGAs; the second, operating at a bandwidth of ~50kHz, is achieved through the CPU, which is possibly running a hard-real-time operating system (RTOS).

 

DSP Partitioning

One issue is that almost any instrument faces the problem of reducing huge amounts of input data from raw sampling to the point of the instrument’s outputs, such as a scope diagram holding 1000 points only, or the frequency-domain plot of a spectrum analyser. The reduction of data from the instrument’s inputs to its outputs is therefore the main job of the embedded digital signal processing.

The combination of an FPGA and CPU therefore enables significant freedom in partitioning elements of the signal processing. Generally, the FPGA handles ultra-fast yet simple DSP operations, whereas the CPU excels at slower, but arbitrarily complex procedural operations. Also, while there have been significant improvements in FPGA development tools in recent years, it is still generally easier to write procedural software to run on the CPU. This partitioning freedom brings another advantage, which is the ability to rapidly prototype a performance-limited but fully functional system. Implementing most of the DSP on the CPU allows prototype demonstrations at early stages of the development project, allowing the transition of the performance-critical part of the DSP to the FPGA for a final product with the same functionality, but with higher performance. Figure 3 shows an example of partitioning the DSP algorithms between the FPGA and the CPU.

 

Figure 3 – DSP algorithm partitioning between the FPGA and CPU

 

During the development cycle, the separation can vary, but as the DSP processing is split, the partially processed data must be transferred between the FPGA and the CPU or vice versa. The bus speed is therefore important to avoid introducing additional processing latency.